Back to results
US 2008/0175062 A1Published application
Integrated flash memory systems and methods for load compensation
AssigneeSilicon Storage Technology, Inc.
InventorHieu Van Tran
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSilicon Storage Technology, Inc.
InventorHieu Van Tran
Estimating the term…
Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:
A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:
A system-on-chip controller memory system comprising:
A system-on-chip controller memory system comprising:
A system-on-chip controller memory system comprising:
A system-on-chip controller memory system comprising:
Dependencies are inferred from the claim text.