Non-volatile memory devices and methods of operating the same

A non-volatile memory device, comprising:

• a plurality of unit cells, each of the unit cells including at least one memory transistor and at least one auxiliary transistor, the at least one memory transistor and the at least one auxiliary transistor being connected in series and arrayed in a matrix,
• the memory transistor including,
• a semiconductor substrate including a source region and a first drain region,
• a first control gate electrode on the substrate, the source region being defined in the substrate at a first side of the first control gate electrode, and
• a first charge storing layer between the semiconductor substrate and the first control gate electrode,
• the auxiliary transistor including,
• a first auxiliary gate electrode at a second side of the first control gate electrode, the first auxiliary gate electrode recessed into the substrate, the first drain region defined in the substrate at a first side of the first auxiliary gate electrode being opposite to the first control gate electrode;
• a plurality of bit lines, each of the bit lines being in a separate row passing through the unit cells such that each bit line is connected to each drain region of each of the plurality of memory transistors in the row;
• and
• a plurality of word lines, each of the word lines being in a separate column passing through the unit cells such that each word line is connected to each control gate electrode of each of the plurality of memory transistors in the column.

A method of operating a non-volatile memory device, the method comprising:

• selecting one or more of a plurality of unit cells to store data into the unit cells, each of the unit cells including at least one memory transistor and at least one auxiliary transistor, the at least one memory transistor and the at least one auxiliary transistor being connected in series and arrayed in a matrix,
• the memory transistor including,
• a semiconductor substrate including a source region and a first drain region,
• a first control gate electrode on the substrate, the source region being defined in the substrate at a first side of the first control gate electrode, and
• a first charge storing layer between the semiconductor substrate and the first control gate electrode,
• the auxiliary transistor including,
• a first auxiliary gate electrode at a second side of the first control gate electrode, the first auxiliary gate electrode recessed into the substrate, the first drain region defined in the substrate at a first side of the first auxiliary gate electrode being opposite to the first control gate electrode,
• wherein the at least one auxiliary transistor in the other unit cells except the selected one or more unit cells are turned off in the program operation.