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US 2008/0174924 A1Published application
Electrostatic discharge (esd) protection device
AssigneeSamsung Electronics Co., Ltd.
InventorsMyoung-Gon KANG, Ki-Whan SONG
Life of this patent
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Abstract
An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.
Claims18
An electrostatic discharge (ESD) protection device formed in a substrate of first conductivity type (FCT), and comprising:
- an Input/Output (I/O) terminal structure comprising;
- a first well region of second conductivity type (SCT) formed in the substrate,
- a first SCT region formed in the first well region and a first FCT region formed in the first well region and spaced apart from the first SCT region, the first SCT region and the first FCT region being connected to an I/O terminal, and
- bridge region of SCT formed in contact with the first well region and the substrate;
- a current discharge structure comprising:
- a second SCT region formed in the substrate and separated from the bridge region by a gate electrode,
- a second well region of SCT region formed in the substrate below the second SCT region,
- a third well region of SCT formed in the substrate and separated from the second well region by a second FCT region formed in the substrate,
- a third SCT region, a third FCT region, and a fourth SCT region spaced apart and formed in the third well region, and
- a fourth FCT region formed in the substrate on a side of the third well region opposite the second FCT region.
7 more elements
A multi-finger electrostatic discharge (ESD) protection device formed in a substrate of first conductivity type (FCT) and comprising:
- a common Input/Output (I/O) terminal structure centered between first and second current discharge structures,
- wherein the common I/O terminal structure comprises;
- a first well region of second conductivity type (SCT) formed in the substrate,
- a first SCT region formed in the first well region,
- dual first FCT regions formed in the first well region and spaced apart on opposite sides of the first SCT region, the first SCT region and the dual first FCT region being connected to an I/O terminal, and
- dual bridge regions of SCT formed in contact with the first well region and the substrate and respectively separated from the first SCT region by one of the dual first FCT regions;
- wherein each one of the first and second current discharge structures comprises:
- a second SCT region formed in the substrate and separated from a respective one of the dual bridge regions by a gate electrode,
- a second well region of SCT region formed in the substrate below the second SCT region,
- a third well region of SCT formed in the substrate and separated from the second well region by a second FCT region formed in the substrate,
- a third SCT region, a third FCT region, and a fourth SCT region spaced apart and formed in the third well region,
- a fourth FCT region formed in the substrate on a side of the third well region opposite the second FCT region;
- and
- a coupling connector electrically coupling the respective second FCT regions of the first and second current discharge structures.
11 more elements
An electrostatic discharge (ESD) protection device fabricated on a semiconductor substrate and having an equivalent circuit, comprising:
- a first junction transistor having a collector, a base and an emitter and a second junction transistor having a collector, a base and an emitter, wherein the collector of the first junction transistor is connected to the base of the second junction transistor and the base of the first junction transistor is connected to the collector of the second junction transistor;
- a first resistor connecting an Input/Output (I/O) terminal to the collector of the first junction transistor, wherein the emitter of the second junction transistor is connected to the I/O terminal;
- an NMOS transistor having a gate connected to a power supply voltage, and a drain and a source respectively connected to the collector and emitter of the first junction transistor;
- second and third series connected resistors connecting the collector of the second junction transistor to the power supply voltage;
- and
- parallel first and second current discharge paths to which the source of the NMOS transistor and the emitter of the first junction transistor are commonly connected so as to discharge current into the power supply voltage.
3 more elements
A multi-finger electrostatic discharge (ESD) protection device fabricated on a semiconductor substrate and having an equivalent circuit, comprising:
- first and second current discharge structures connected to a common Input/Output (I/O) terminal, wherein each one of the first and second current discharge structures comprises;
- a first junction transistor having a collector, a base and an emitter and a second junction transistor having a collector, a base and an emitter, wherein the collector of the first junction transistor is connected to the base of the second junction transistor and the base of the first junction transistor is connected to the collector of the second junction transistor;
- a first resistor connecting the I/O terminal to the collector of the first junction transistor, wherein the emitter of the second junction transistor is connected to the I/O terminal;
- an NMOS transistor having a gate connected to a power supply voltage, and a drain and a source respectively connected to the collector and emitter of the first junction transistor;
- second and third series connected resistors connecting the collector of the second junction transistor to the power supply voltage;
- and
- parallel first and second current discharge paths to which the source of the NMOS transistor and the emitter of the first junction transistor are commonly connected so as to discharge current into the power supply voltage;
- and
- a coupling connector electrically connected between respective second and third series connected resistors in each one of the first and second current discharge structures.
6 more elements
Dependencies are inferred from the claim text.