Static semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsAtsushi Kawasumi, Tetsu Morooka
Life of this patent
Estimating the term…
Abstract
A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in the substrate, a channel region of the first transfer transistor is offset with respect to the second diffusion layer toward the first storage node, and the offset part functions as a resistor.
Claims20
A static semiconductor memory device comprising:
- first and second storage nodes configured to store complementary data;
- a first transfer transistor connected between the first storage node and a first bit line;
- and
- a second transfer transistor connected between the second storage node and a second bit line,
- wherein each of the first and second transfer transistors is provided with a first diffusion layer connected to the first or second bit line and including an extension region, and a second diffusion layer connected to the first or second storage node and including an extension region, and
- the first diffusion layer is provided in a surface region of a substrate, and the second diffusion layer is provided in a bottom part of a recess provided in the substrate.
A static semiconductor memory device comprising:
- first and second storage nodes configured to store complementary data;
- a first transfer transistor connected between the first storage node and a first bit line;
- and
- a second transfer transistor connected between the second storage node and a second bit line,
- wherein each of the first and second transfer transistors is provided with a first diffusion layer connected to the first or second bit line and including an extension region, and a second diffusion layer connected to the first or second storage node and including an extension region, and
- the first diffusion layer is provided in a surface region of a substrate, and the second diffusion layer is provided in a semiconductor layer provided on the substrate.
A static semiconductor memory device comprising:
- first and second storage nodes configured to store complementary data;
- a first transfer transistor connected between the first storage node and a first bit line;
- and
- a second transfer transistor connected between the second storage node and a second bit line, wherein
- each of the first and second transfer transistors is provided with a first source/drain region connected to the first or second bit line, and a second source/drain region connected to the first or second storage node, and the resistance of the second source/drain region is set greater than the resistance of the first source/drain region.
Dependencies are inferred from the claim text.