US 2008/0173915 A1Published application

Single-gate non-volatile memory and operation method thereof

OwnerHsin-Chang Lin, Wen-Chien Huang +3inventors

InventorsHsin-Chang Lin, Wen-Chien Huang, Ming-Tsang Yang, Hao-Cheng Chang, Cheng-Ying Wu

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Abstract

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Claims10

Dependent claims

A single-gate non-volatile memory, comprising:

a semiconductor substrate;
a transistor, having a first dielectric layer, a first electrically-conductive gate and a plurality of first ion-doped regions, said first dielectric layer disposed on the surface of said semiconductor substrate, said first electrically-conductive gate stacked on said first dielectric layer, said first ion-doped regions separately disposed at both sides of said first electrically-conductive gate and respectively functioning as the source and the drain;
and
a capacitor structure having a second dielectric layer, a second electrically-conductive gate and a second ion-doped region, said second dielectric layer disposed on the surface of said semiconductor substrate said second electrically-conductive gate, stacked on said second dielectric layer, said second ion-doped region disposed at one side of said second dielectric layer;
wherein said first electrically-conductive gate and said second electrically-conductive gate being separated and electrically interconnected to form a single floating gate.

2 more elements

Dependencies are inferred from the claim text.