Method and structure for reducing prior level edge interference with critical dimension measurement
AssigneeInternational Business Machines Corporation
InventorsAlexander L. Martin, Eric P. Solecky
Life of this patent
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Abstract
A method for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures includes forming a test structure in a kerf region of a semiconductor wafer, the test structure including at least a via structure and a trench structure in contact with the via structure. The via structure is formed in accordance with a critical dimension associated with a corresponding via structure in a circuit region of the semiconductor wafer, and the trench structure is formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with a corresponding trench structure in a circuit region of the semiconductor wafer.
Claims6
A test structure for reducing edge effect interference with critical dimension (CD) measurement of semiconductor via structures, comprising:
- a plurality of lower trenches and a plurality of upper trenches formed in a kerf region of a semiconductor wafer;
- a plurality of vias formed between said lower and upper trenches;
- said vias formed in accordance with a critical dimension associated with corresponding vias in a circuit region of the semiconductor wafer;
- and
- said lower and upper trenches formed in accordance with a widened dimension with respect to a minimum ground rule dimension associated with corresponding lower and upper trenches in a circuit region of the semiconductor wafer.
Dependencies are inferred from the claim text.