Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorHyoung-Seub RHIE
Life of this patent
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Abstract
There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.
Claims25
A semiconductor memory device comprising:
- first and second active areas extending in a first direction on a semiconductor substrate;
- first and second split word lines extending in a second direction on the semiconductor substrate;
- a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas;
- a first variable resistance element formed on the first active area between the first and second split word lines;
- a second variable resistance element formed on the second active area between the first and second split word lines;
- and
- first and second bit lines extending in the first direction, and respectively coupled to the first and second variable resistance elements.
A semiconductor memory device comprising:
- first and second split word lines formed on a semiconductor substrate;
- a common source line having a fishbone antenna-like shape and including an axis source line intersecting the first and second split word lines and a plurality of spine source lines protruding from the axis source line;
- and
- first and second bit lines intersecting the first and second split word lines.
A semiconductor memory device comprising:
- a first memory cell comprising first and second access elements and a first variable resistance element coupled between the first and second access elements;
- a second memory cell comprising third and fourth access elements and a second variable resistance element coupled between the third and fourth access elements;
- a first bit line coupled to the first variable resistance element and a second bit line coupled to the second variable resistance element;
- a first split word line coupled to the first and third access elements and a second split word line coupled to the second and fourth access elements;
- and
- a common source line coupled to the first, second, third and fourth access elements.
Dependencies are inferred from the claim text.