Multi-chip package

A multi-chip package, comprising:

• a substrate, having a first surface;
• a first chip, disposed on the first surface and having a first orthogonal projection on the first surface;
• a plurality of conductive bodies, disposed and electrically connected between the first chip and the first surface;
• a second chip, disposed on the first surface and having a second orthogonal projection on the first surface, wherein at least part of the first chip is between the second chip and the substrate, and the first orthogonal projection at least overlaps the second orthogonal projection;
• a plurality of first conductive studs, disposed and electrically connected between the second chip and the first surface;
• a third chip, disposed on the first surface and having a third orthogonal projection on the first surface, wherein at least part of the second chip is between the third chip and the substrate, and the second orthogonal projection at least overlaps the third orthogonal projection;
• and
• a plurality of second conductive studs, disposed and electrically connected between the third chip and the first surface.

A multi-chip package, comprising:

• a substrate, having a first surface;
• a first chip, disposed on the first surface and having a first orthogonal projection on the first surface;
• a second chip, disposed on the first surface and having a second orthogonal projection on the first surface, wherein part of the first chip is between the second chip and the substrate, and the first orthogonal projection at least overlaps the second orthogonal projection;
• a plurality of first conductive bodies, disposed and electrically connected between the first chip and the second chip, and
• a plurality of first conductive studs, disposed and electrically connected between the second chip and the first surface.

A multi-chip package, comprising:

• a substrate, having a first surface;
• a first chip, disposed on the first surface and having a first orthogonal projection on the first surface;
• a plurality of first conductive bodies, disposed and electrically connected between the first chip and the first surface;
• a second chip, disposed on the first surface and having a second orthogonal projection on the first surface;
• a plurality of second conductive bodies, disposed and electrically connected between the second chip and the first surface;
• a third chip, disposed on the first surface and having a third orthogonal projection on the first surface, wherein the first chip and the second chip are between the third chip and the substrate, and the third orthogonal projection at least overlaps the first orthogonal projection and the second orthogonal projection;
• and
• a plurality of conductive studs, disposed and electrically connected between the third chip and the first surface.