Heterojunction bipolar transistor (hbt) with self-aligned sub-lithographic metal-semiconductor alloy base contacts
AssigneeInternational Business Machines Corporation
InventorsGuy M. Cohen, Francois Pagette
Life of this patent
Estimating the term…
Abstract
A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
Claims20
A heterojunction bipolar transistor (HBT) comprising:
- a stack including, from top to bottom, an emitter, a base and a collector;
- an extrinsic base adjacent to said base wherein a lateral dimension of said extrinsic base is defined by the footprint of a sacrificial spacer;
- a metal-semiconductor alloy region over said extrinsic base;
- and
- buried conductive lines connecting to an edge of said metal-semiconductor alloy region.
A heterojunction bipolar transistor (HBT) comprising:
- a stack including, from top to bottom, an emitter, a base and a collector;
- an extrinsic base adjacent to said base wherein lateral dimension of said extrinsic base is defined by the footprint of a sacrificial spacer;
- a silicide region over said extrinsic base;
- and
- buried silicide lines connecting to the edge of said silicide region.
A method of forming a heterojunction bipolar transistor (HBT) comprising:
- forming a collector region isolated by a shallow trench isolation (STI) oxide;
- forming a base layer over the collector and said STI oxide, wherein the base layer is single-crystalline over the collector and poly-crystalline over the STI oxide;
- forming an emitter over said base layer, wherein said emitter is fully enclosed within said collector region;
- forming oxide sidewall spacers over said emitter sidewalls;
- forming sacrificial sidewalls spacers adjacent to said emitter;
- defining an extrinsic base region by etching unmasked regions of said base layer;
- forming a planarizing first dielectric;
- recessing said first dielectric below an upper surface of said emitter;
- removing said sacrificial sidewall spacers to expose an upper surface of said extrinsic base region;
- depositing a metal and reacting said metal to form a metal-semiconductor alloy;
- depositing a second dielectric over said metal and said metal-semiconductor alloy and planarizing second dielectric by chemical mechanical polishing;
- and
- etching selectively said metal over said oxide sidewall spacers.
Dependencies are inferred from the claim text.