US 2008/0164468 A1 · Reinforced semiconductor structures

Abstract

Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality of first non-dielectric pillars are formed in the topmost layer of the dielectric layers in the scribe line region and surround the test pad along a periphery. A plurality of second non-dielectric pillars and first vias are formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively.

Claims20

Dependent claims

A reinforced semiconductor structure, comprising:

a semiconductor wafer comprising a plurality of low-k dielectric layers formed thereon;
at least one scribe line region defined over the semiconductor wafer, separating at least two active regions formed over the semiconductor wafer;
a plurality of first non-dielectric pillars formed in the topmost layer of the low-k dielectric layers in the scribe line region, surrounding the test pad along a periphery;
and
a plurality of second non-dielectric pillars and first vias formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively

2 more elements

A reinforced semiconductor structure, comprising:

a semiconductor wafer comprising a plurality of low-k dielectric layers formed thereon;
at least one scribe line region defined over the semiconductor wafer, separating at least two active regions formed over the semiconductor wafer;
at least one test element formed in the scribe line region, passing through the low-k dielectric layers therein and having a test pad exposed by a topmost low-k layer of the low-k dielectric layers therein, wherein the test pad comprises a recess on opposing sides thereof;
a plurality of first non-dielectric pillars formed in the topmost layer of the low-k dielectric layers in the scribe line region, surrounding the test pad along a frontier thereof;
and
a second non-dielectric pillar formed at the recess and in the topmost low-k layer of the low-k dielectric layers, electrically isolated from the test pad.

3 more elements

Dependencies are inferred from the claim text.

Reinforced semiconductor structures

Life of this patent

Reinforced semiconductor structures

Life of this patent

Abstract

Claims20