Packaging implementation while mitigating threshold voltage shifting
AssigneeTexas Instruments Incorporated
InventorsLixia Li, He Lin
Life of this patent
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Abstract
One or more passivation layers are added to the end of a semiconductor process flow to provide additional protection for devices (e.g., transistors) formed during the process. An additional layer is then formed and/or an anneal is performed to mitigate threshold voltage shifting that may be induced by the passivation layers. Mitigation of threshold voltage shifting increases the life expectancy of devices (e.g., transistors) formed during the process, which in turn mitigates yield loss by facilitating predictable or otherwise desirable behavior of the devices (e.g., transistors).
Claims20
A method for implementing passivation layers in a semiconductor fabrication process while mitigating threshold voltage shifting that may result there-from, comprising:
- forming one or more back end layers of conductive, semi-conductive and/or non-conductive/dielectric layers over a semiconductor device formed in/on a semiconductor substrate;
- forming a first layer of dielectric passivation material over the back end layers;
- forming a first layer of conductive material over the first layer of dielectric passivation material;
- forming a second layer of dielectric passivation material over the first layer of conductive material;
- and
- forming a fourth layer of dielectric passivation material over the second layer of dielectric passivation material.
A method for implementing passivation layers in a semiconductor fabrication process while mitigating threshold voltage shifting that may result there-from, comprising:
- forming one or more back end layers of conductive, semi-conductive and/or non-conductive/dielectric layers over a semiconductor device formed in/on a semiconductor substrate;
- forming a first layer of dielectric passivation material over the back end layers;
- forming a first layer of conductive material over the first layer of dielectric passivation material;
- forming a second layer of dielectric passivation material over the first layer of conductive material;
- and
- performing an anneal to relax tension or compression in the first and second layers of dielectric passivation material.
A semiconductor passivation arrangement, comprising:
- one or more back end layers of conductive, semi-conductive and/or non-conductive/dielectric layers formed over a semiconductor device formed in/on a semiconductor substrate;
- a first layer of dielectric passivation material formed over the back end layers;
- a first layer of conductive material formed over the first layer of dielectric passivation material;
- a second layer of dielectric passivation material formed over the first layer of conductive material;
- and
- a fourth layer of dielectric passivation material formed over the second layer of dielectric material.
Dependencies are inferred from the claim text.