Method of forming silicided gates using buried metal layers
AssigneeTexas Instruments Incorporated
InventorsSteven Arthur Vitale, Shaofeng Yu
Life of this patent
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Abstract
A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.
Claims20
A method of fabricating a semiconductor device, comprising:
- forming a gate stack, wherein the gate stack comprises a gate dielectric layer, a first silicon layer adjacent to a substrate;
- a first metal layer over the first silicon layer;
- and a second silicon layer over the first metal layer;
- patterning the gate stack;
- and
- performing a silicidation process to form metal and silicon alloy regions in the patterned gate stack, wherein at least one alloy region is formed adjacent to the substrate.
The method of claim 27 wherein the first and second metal layers comprise different metals.
A method of forming a silicided gate, comprising:
- forming a first silicon layer adjacent to a gate dielectric layer;
- forming a first metal layer over the first silicon layer;
- forming a second silicon layer over the first metal layer;
- and
- performing a silicidation process to form metal and silicon alloy regions in the gate, wherein at least one alloy region is formed adjacent to the gate dielectric layer.
A semiconductor device, comprising:
- a substrate;
- a gate dielectric layer positioned adjacent to the substrate;
- and
- a gate stack positioned over the gate dielectric, the gate stack comprising:
- a first metal and silicon alloy layer positioned adjacent to the gate dielectric layer,
- a silicon layer position over the first alloy layer, and
- a second metal and silicon alloy layer positioned adjacent to the silicon layer.
Dependencies are inferred from the claim text.