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US 2008/0157187 A1Published application
Bit lines for semiconductor devices
AssigneeSpansion LLC
InventorsWeidong QIAN, Mark T. RAMSBEY, Tazrien KAMAL
Life of this patent
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Abstract
A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
Claims2
A memory device, comprising:
- a substrate;
- a first dielectric layer formed over the substrate;
- a charge storage element formed over the first dielectric layer;
- a second dielectric layer formed over the charge storage element;
- a control gate formed over the second dielectric layer;
- and
- a bit line formed in the substrate, the bit line comprising:
- an n-type impurity region formed to a first depth below an upper surface of the substrate and having a first width, and
- a p-type impurity region formed to a second depth below the upper surface of the substrate and having a second width, the second width being greater than the first width.
6 more elements
2-20. (canceled)
Dependencies are inferred from the claim text.