Method of fabricating flash memory device
AssigneeDongbu HiTek Co., Ltd.
InventorCheon Man Sim
Life of this patent
Estimating the term…
Abstract
A flash memory device including a cell region and a logic region formed over a semiconductor substrate; a pair of stacked gates formed spaced apart over the cell region; a pair of first spacers formed over the cell region in direct contact with at least one side of the stacked gates; a pair of gate electrodes formed spaced apart over the logic region; a pair of second spacers formed over the logic region in direct contact with at least one side of the gate electrodes; a first photoresist layer formed over the cell area between the first spacers and a second photoresist layer formed over the logic area between the second spacers, the second photoresist layer having a predetermined thickness sufficient to protect the second spacers.
Claims20
A method comprising:
- forming a pair of stacked gates spaced apart over a cell region of a semiconductor substrate;
- forming a pair of first spacers over the cell region in direct contact with at least one side of the stacked gates;
- forming a pair of gate electrodes spaced apart over a logic region of the semiconductor substrate;
- forming a pair of second spacers over the logic region in direct contact with at least one side of the gate electrodes;
- coating a first photoresist layer over the cell area between the first spacers and a second photoresist layer over the logic area between the second spacers, wherein the second photoresist layer is formed to a predetermined initial thickness sufficient to cover at least a portion of the second spacers;
- hardening the first photoresist layer and the second photoresist layer;
- and then
- reducing the initial thickness of the second photoresist layer using an etching process to a final thickness sufficient to protect the second spacers.
An apparatus comprising:
- a cell region and a logic region formed over a semiconductor substrate;
- a pair of stacked gates formed spaced apart over the cell region;
- a pair of first spacers formed over the cell region in direct contact with at least one side of the stacked gates;
- a pair of gate electrodes formed spaced apart over the logic region;
- a pair of second spacers formed over the logic region in direct contact with at least one side of the gate electrodes;
- and
- a first photoresist layer formed over the cell area between the first spacers and a second photoresist layer formed over the logic area between the second spacers,
- wherein the second photoresist layer has a predetermined thickness sufficient to protect the second spacers.
An apparatus comprising:
- a logic region provided over a semiconductor substrate;
- a pair of gate electrodes formed over the logic region;
- a pair of spacers formed over the logic region in direct contact with a respective one of the gate electrodes;
- and
- a photoresist layer formed between and in contact with the pair of spacers, wherein the photoresist layer has a predetermined thickness sufficient to protect the second spacers.
Dependencies are inferred from the claim text.