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US 2008/0157075 A1Published application
Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias
AssigneeGlobalfoundries Inc.
InventorsFrank Feustel, Kai Frohberg, Thomas Werner
Life of this patent
Estimating the term…
Abstract
By providing vias of increased mass flow blocking capability next to respective line segments of an electromigration test structure, the reliability of respective assessments may be enhanced, since electromigration-induced void formation in the test line segment under consideration may be efficiently decoupled from metal diffusion of neighboring test areas of the test structure.
Claims20
A chain structure for electromigration tests, comprising:
- a first line segment and a second line segment formed in a first metallization layer located above a semiconducting substrate;
- a first via connected to said first line segment, said first via having a first mass flow blocking capability at a bottom surface of said first via;
- a second via connected to said second line segment, said second via having a second mass flow blocking capability, said first mass flow blocking capability being less than said second mass flow blocking capability;
- and
- a third line segment formed in a second metallization layer and connected to at least one of said first and second vias.
2 more elements
A test structure for estimating electromigration effects in a metallization layer of a semiconductor device, the test structure comprising:
- a first line segment having a first width and formed in a first metallization layer;
- a second line segment having a second width greater than said first width, said second line segment formed in said first metallization layer;
- a first via connected to said first line segment;
- a second via connected to said second line segment;
- and
- a third line segment formed in a second metallization layer and connected to at least one of said first and second vias.
3 more elements
A method, comprising:
- forming a trench and a via opening connected thereto for a first line segment and a first via of a test structure in a first metallization layer formed above a substrate, said substrate comprising a plurality of semiconductor devices;
- forming a trench and a via opening connected thereto for a second line segment and a second via of said test structure;
- and
- forming a conductive barrier layer in said trenches and via openings by establishing a first deposition rate at said first via and a second deposition rate at said second via, said first deposition rate being less than said second deposition rate.
1 more element
Dependencies are inferred from the claim text.