Data Processing Apparatus Including Reconfigurable Logic Circuit

A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising:

• a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application;
• and
• a functional unit for generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application.

A method of generating hardware control information for controlling a reconfigurable logic circuit, the method comprising the steps of:

• generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application;
• and
• generating the hardware control information, the hardware control information including a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits onto the logic circuit individually and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application.

A recording medium on which hardware control information for controlling a data processing apparatus including a reconfigurable logic circuit is recorded, the hardware control information comprising:

• a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the a plurality of cycle-based circuits realizing a function in each cycle for executing an application;
• and
• configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application.