Data Processing System

A data processing system comprising:

• a logic circuit region where circuits are dynamically reconfigurable;
• a load unit for obtaining an architecture code, the architecture code including object circuit information for mapping an object circuit that is at least part of a circuit for executing an application onto part of the logic circuit region, interface circuit information for mapping an interface circuit in contact with the object circuit onto the logic circuit region, and boundary condition to be realized in the interface circuit;
• a mapping unit for mapping the object circuit and the interface circuit in contact with the object circuit onto the logic circuit region according to the object circuit information and the interface circuit information of the architecture code;
• and
• a behavior control unit for controlling the interface circuit according to the boundary condition of the architecture code.

A method for generating an architecture code for controlling a data processing system including a logic circuit region where circuits are dynamically reconfigurable, the architecture code including object circuit information for mapping an object circuit that is at least part of a circuit for executing an application onto part of the logic circuit region, interface circuit information for mapping an interface circuit in contact with the object circuit onto the logic circuit region, and boundary condition to be realized in the interface circuit, the method comprising:

• a step of generating object circuit information by dividing a netlist of the circuit for executing the application and resolving place and route issues within divided ranges of the netlist;
• a step of generating interface circuit information from information in the netlist for forming boundary of the object circuit configured by the object circuit information;
• and
• a step of converting the netlist into a group of object circuits, resolving place and route issues among the object circuits, and generating boundary condition of interface circuits of respective object circuits.