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AssigneeQUALCOMM Incorporated
InventorsBrian Michael Stempel, Rodney Wayne Smith
Estimating the term…
In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
A method of forming an address to index every line in a branch history table (BHT) in a variable length instruction set processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, whereby each instruction set execution mode has a different native index address, comprising:
A method of forming line and counter index addresses to access every counter in a branch history table (BHT) in a variable length instruction set processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, comprising:
A method of operating a branch history table (BHT) comprising a plurality of counters in a variable length instruction set processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, comprising:
A processor, comprising:
Dependencies are inferred from the claim text.