Power control scheme for a power amplifier

A transceiver comprising:

• an interface to receive transmit power control information from a processor;
• a memory to store first parameter information for a first burst of a data transmission from the transceiver;
• and
• a controller coupled to the interface and the memory to receive the transmit power control information and the first parameter information and to determine second parameter information for a second burst of the data transmission based on the first parameter information and the transmit power control information, the second burst following the first burst.

An article comprising a machine-readable medium including instructions that enable a system to:

• receive a detected power level of a first burst of a multi-slot burst communication from a power amplifier (PA);
• determine a power level update for a second burst of the multi-slot burst communication based at least in part on the detected power level of the first burst;
• and
• provide the second burst to the PA responsive to the power level update.

A system comprising:

• a transceiver having an interface to receive power control information from a processor, and a controller coupled to the interface to determine a power control update for a succeeding burst of a multi-slot burst communication based on the power control information and feedback information from a preceding burst of the multi-slot burst communication, the controller to determine the power control update during the preceding burst and to apply the power control update during an inter-burst period between the preceding burst and the succeeding burst;
• a power amplifier coupled to the transceiver to provide the feedback information;
• and
• an antenna coupled to the power amplifier to transmit the multi-slot burst communication.