Damascene Contact Structure for Integrated Circuits
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsJian Hui YE, Mei Sheng ZHOU
Life of this patent
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Abstract
Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.
Claims13
A method of fabricating an integrated circuit comprising the steps of:
- providing a semiconductor body having a transistor structure with isolation, gate and spacers and silicide contact region;
- forming an interconnecting dielectric layer (ICD) including first and second dielectric layers on the semiconductor body, wherein the first dielectric layer is an interlayer dielectric (ILD) comprising oxide or low-k dielectric material and the second dielectric layer comprises low-k dielectric material;
- forming a hard mask over the second dielectric layer;
- forming bottom antireflective coating (BARC) and photoresist layers over the hard mask;
- patterning the photoresist and BARC layers;
- patterning the hard mask to form a contact opening by performing a first dry etch;
- patterning the first and second dielectric layers using the hard mask as an etch mask by a second dry etching to form a contact via;
- forming a sacrificial layer over the semiconductor body which fills the via and covers a surface of the second dielectric layer;
- forming second BARC and photoresist layers on the sacrificial layer;
- patterning the second BARC and photoresist layers;
- repatterning the hard mask to form a trench opening by performing a third dry etch;
- patterning the ICD layer using the repatterned hard mask to form trench and to expose silicide contact region by performing a fourth dry etch, the fourth dry etch forming a dual damascene structure;
- and
- forming metal interconnect in the dual damascene structure.
A method for forming interconnections in an IC comprising:
- providing a substrate having a contact region;
- forming a dielectric layer over the substrate;
- depositing and patterning a hard mask layer on the dielectric layer;
- etching the dielectric layer using the patterned hard mask, wherein etching leaves a dielectric plug at a lower portion of the dielectric layer covering the contact regions;
- repatterning the patterned hard mask,
- etching the dielectric layer using the repatterned hard mask to form trenches in an upper portion of the dielectric layer;
- and
- removing the dielectric plug to expose the contact region.
A method for forming interconnections in an IC comprising:
- providing a substrate having a contact region and a dielectric layer over the substrate in which an interconnection is formed to the contact region;
- depositing a hard mask, the hard mask having a high etch selectivity to the dielectric layer which enables a reduction in thickness of a mask layer used for forming interconnect structure to produce an increase in CD control;
- and
- forming a dual damascene structure in the dielectric layer with the hard mask as an etch mask.
A method for forming interconnections comprising:
- forming an interconnecting barrier which lines a cavity disposed on a substrate;
- forming a liner layer on the substrate over the interconnecting barrier;
- filling the cavity with a conductive material;
- and
- annealing the substrate, wherein the annealing forms a secondary liner layer from a reaction between the conductive material and the liner layer.
Dependencies are inferred from the claim text.