Manufacturing method of a semiconductor device
AssigneeRenesas Technology Corp.
InventorsIsao Miyashita, Yuji Fujii, Hajime Ebara, Katsuo Ishizaka, Norio Hosoya, Hidekazu Okuda
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AssigneeRenesas Technology Corp.
InventorsIsao Miyashita, Yuji Fujii, Hajime Ebara, Katsuo Ishizaka, Norio Hosoya, Hidekazu Okuda
Estimating the term…
Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.
A manufacturing method of a semiconductor device, comprising the steps of:
A manufacturing method of a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.