Memory device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorWook-Hyoung Lee
Life of this patent
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Abstract
In a memory device and a method of manufacturing the memory device, a source contact connected to a common source line may be formed on a drain region instead of a source region. A transistor having a negative threshold voltage may be formed between the source region and the drain region. A channel of the transistor may be formed. Because the source contact is formed on the drain region, the size of the source region may be reduced. An integration degree of the memory device may be improved. A control gate may linearly extend in a second direction because the source contact is not formed on the source region.
Claims15
A memory device comprising:
- a first transistor including a first source region, a first drain region and a first channel region between the first source region and the first drain region, the first channel region being doped with a P-typed impurity having a first concentration;
- a second transistor including a second source region, a second drain region and a second channel region, the second channel region being doped with a P-typed impurity having a second concentration, the second concentration being substantially lower than the first concentration;
- a common source extending in a first direction to be electrically connected to the first source region and the second source region;
- a drain contact on the first drain region;
- and
- a source contact on the second drain region.
A method of manufacturing a memory device, the method comprising:
- forming a first P-typed impurity region and a second P-typed impurity region that have a first P-typed impurity concentration by implanting P-typed impurities into an upper portion of the semiconductor substrate;
- selectively implanting the P-typed impurities into a surface portion of the second P-typed impurity region to selectively form a third P-typed impurity region having a second concentration substantially larger than the first concentration at the surface portion of the second P-typed impurity region;
- subsequently forming a floating gate, an ONO layer pattern and a control gate on the first P-typed impurity region and the third P-typed impurity region;
- and
- implanting N-typed impurities into the first P-typed impurity region and the third P-typed impurity region to form a first source region, a first drain region, a second source region and a second drain region, the first source region and the first drain region being formed at the second P-typed impurity region below both sides of the floating gate, the second source region and the second drain region being formed at the first P-typed impurity region below both sides of the floating gate;
- forming a drain contact on the first drain region;
- and
- forming a source contact on the second drain region.
Dependencies are inferred from the claim text.