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US 2008/0076212 A1Published application
Structure and layout of a fet prime cell
AssigneeInternational Business Machines Corporation
InventorsBasanth JAGANNATHAN, John Pekarik, Christopher Schnabel
Life of this patent
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Abstract
Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
Claims20
A method of making a semiconductor device, comprising the steps of:
- forming a source and a drain in a substrate;
- forming a gate on the substrate between the source and drain;
- forming a substrate contact in electrical contact with the source;
- and
- forming an electrical contact to the source, drain and gate, and the substrate.
2 more elements
A method of fabricating a device, comprising the steps of:
- forming an active region including a source, drain and gate region;
- and
- forming a collection source configured for shielding electrical noise external to the active region.
Dependencies are inferred from the claim text.