Inter-Packet Gap Network Clock Synchronization
AssigneeFuturewei Technologies, Inc.
InventorSerge Francois Fourcand
Life of this patent
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Abstract
A network component comprising at least one processor configured to implement a method comprising adding a clock synchronization data to a data stream comprising a plurality of Ethernet packets, wherein the clock synchronization data is located in a gap between two of the Ethernet packets. Also disclosed is a method comprising adding a clock synchronization data to a gap between a plurality of Ethernet packets in a data stream, wherein the clock synchronization data comprises a timestamp, a first bit that indicates whether the clock synchronization data is a request or an acknowledgement, and a second bit that indicates a requested operational mode.
Claims20
A network component comprising:
- at least one processor configured to implement a method comprising:
- adding a clock synchronization data to a data stream comprising a plurality of Ethernet packets,
- wherein the clock synchronization data is located in a gap between two of the Ethernet packets.
A method comprising:
- adding a clock synchronization data to a gap between a plurality of Ethernet packets in a data stream, wherein the clock synchronization data comprises:
- a timestamp;
- a first bit that indicates whether the clock synchronization data is a request or an acknowledgement;
- and
- a second bit that indicates a requested operational mode.
An Ethernet node comprising:
- at least one processor configured to implement a method comprising:
- recognizing the reception of a data stream from an upstream node, wherein the data stream comprises a plurality of Ethernet packets and a synchronization request comprising a timestamp;
- synchronizing a clock with the timestamp;
- and
- promoting the transmission of a response to the upstream node,
- wherein the data stream has the same bandwidth as a data stream does not have the synchronization request and the timestamp.
Dependencies are inferred from the claim text.