Driving circuit and organic light emitting diode display device thereof

A data driver, comprising:

• a shift register unit adapted to sequentially output control signals;
• a latch unit adapted to output parallel digital data signals input in series to correspond to the control signal;
• a D/A converter unit adapted to convert the digital data signals to a data voltages;
• and
• a buffer unit amplifying the data voltages, wherein the D/A converter unit includes:
• a first decoder adapted to output a plurality of first decoding signals using upper bits of the digital data signals;
• a switch unit adapted to select a first reference voltage and second reference voltage from a plurality of reference voltages corresponding to the plurality of first decoding signals, the second reference voltage being lower than the first reference voltage, two first decoding signals out of the plurality of first decoding signals selecting identical first and second reference voltages;
• a second decoder adapted to output a plurality of second decoding signals using lower bits of the digital data signal;
• and
• a plurality of voltage distribution units adapted to receive and distribute the first reference voltage and the second reference voltage, wherein one voltage distribution unit includes a data voltage generation unit adapted to receive two of the second decoding signals to generate a data voltage.

An organic light emitting diode display device, comprising:

• a pixel unit adapted to receive a data voltage and a scan signal;
• a data driver adapted to generate the data voltage;
• and
• a scan driver adapted to generate the scan signal, wherein the data driver includes:
• a first decoder adapted to output a plurality of first decoding signals using upper bits of a digital data signal;
• a switch unit adapted to select a first reference voltage and a second reference voltage from a plurality of reference voltages corresponding to a the plurality of first decoding signals, the second reference voltage being lower than the first reference voltage, two first decoding signals out of the plurality of the first decoding signals selecting identical first and second reference voltages;
• a second decoder adapted to output a plurality of second decoding signals using lower bits of the digital data signal;
• and
• a plurality of voltage distribution units adapted to receive and distribute the first reference voltage and the second reference voltage, wherein one voltage distribution unit includes a data voltage generation unit for receiving two second decoding signals to generate a data voltage.