Apparatus and method to reduce jitter in a phase locked loop
AssigneeBroadcom Corporation
InventorYonghua Cong
Life of this patent
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Abstract
A circuit and method to reduce jitter and/or noise in a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) control signal is tapped and filtered to create a low-noise, filtered VCO control signal. The filtered and unfiltered control signals are individually weighted and then combined to create a modified VCO control signal which reduces the jitter and/or the noise by reducing an effect of VCO gain on the jitter and/or the noise.
Claims20
A circuit that reduces jitter in a phase-locked loop (PLL), comprising:
- a filter having an input and an output, wherein said filter is part of the PLL;
- and
- a summation circuit coupled to said filter input and said filter output, wherein said summation circuit combines a part of a filter output signal and a part of a filter input signal to provide a VCO control signal that reduces the jitter.
A method to reduce jitter in a phase-locked loop (PLL), comprising:
- filtering a voltage controlled oscillator (VCO) fast control voltage to produce a slow control voltage;
- and
- controlling a VCO in part with said VCO fast control voltage and in part with said slow control voltage to reduce the jitter.
A circuit that reduces phase-locked loop (PLL) jitter, comprising:
- means for filtering a voltage controlled oscillator (VCO) fast control voltage to produce a slow control voltage;
- and
- means for controlling a VCO in part with said VCO fast control voltage and in part with said slow control voltage to reduce the jitter.
Dependencies are inferred from the claim text.