Current source circuit having a dual loop that is insensitive to supply voltage

A current source circuit that is insensitive to supply voltage comprising:

• a first current mirror having a first PMOS transistor and a second PMOS transistor coupled to each other by a gate to form a gate connection node;
• a second current mirror cascoding with the first current mirror and having a first NMOS transistor and a second NMOS transistor coupled to each other by a gate, wherein a connection node of the first and second NMOS transistors is further coupled to a drain of the first NMOS transistor, a drain of the first NMOS transistor is coupled to a drain of the first PMOS transistor to form a first drain connection node, and a drain of the second NMOS transistor is coupled to drain of the second PMOS transistor to form a second drain connection node
• a third PMOS transistor comprising a gate and a drain both coupled together to the gate connection node of the first current mirror;
• a third NMOS transistor comprising a drain coupled to the drain of the third PMOS transistor to form a third drain connection node and a gate coupled to the second drain connection node of the second PMOS transistor and the second NMOS transistor.