Stacked semiconductor package and method of manufacturing the same

A stacked semiconductor package comprising:

• upper and lower semiconductor packages sequentially stacked,
• wherein each of the upper and lower semiconductor packages comprises:
• a semiconductor chip;
• a plurality of inner leads comprising upper surfaces and bottom surfaces, the inner leads electrically connected to the semiconductor chip;
• an encapsulant covering the semiconductor chip and the inner leads;
• and
• a plurality of outer leads connected to the inner leads and extending outside the encapsulant, wherein the upper surfaces of the upper and lower semiconductor packages are fixed to the encapsulant, portions of the bottom surfaces are exposed from the encapsulant, and the outer leads of the upper semiconductor package are formed toward the lower semiconductor package to be electrically connected to the outer leads of the lower semiconductor package.

A method of manufacturing a semiconductor package, the method comprising:

• providing a lower semiconductor package including a semiconductor chip, a plurality of inner leads electrically connected to the semiconductor chip, and an encapsulant covering the semiconductor chip and inner leads;
• providing an upper semiconductor package including a semiconductor chip, a plurality of inner leads electrically connected to the semiconductor chip, an encapsulant covering the semiconductor chip and inner leads, and a plurality of outer leads extending from the inner leads;
• bending the outer leads of the upper semiconductor package in a downward manner;
• stacking the upper semiconductor package on the lower semiconductor package;
• and
• electrically connecting the outer leads of the upper semiconductor package to the inner leads of the lower semiconductor package.