Semiconductor memory and method for manufacturing a semiconductor memory

A method for manufacturing a semiconductor memory comprising:

• forming a first buried insulating film on a semiconductor substrate;
• forming a second buried insulating film, which is different material from the first buried insulating film, on the first buried insulating film;
• exposing a part of a surface of the semiconductor substrate by removing a part of the first and second buried insulating films;
• burying a first semiconductor layer on the exposed part of the semiconductor substrate so that a horizontal level of the surface of the first semiconductor layer coincides with a horizontal level of a surface of the second buried insulating film;
• depositing a second semiconductor layer on the first semiconductor layer and the second buried insulating film;
• depositing a first insulating layer on the second semiconductor layer;
• depositing an electric charge storage layer on the first insulating layer;
• depositing a second insulating layer on the electric charge storage layer;
• depositing a gate electrode layer on the second insulating layer;
• and
• forming source and drain regions of memory cell transistors so as to implement a cell unit by an arrangement of the memory cell transistors in the second semiconductor layer.

A method for manufacturing a semiconductor memory comprising:

• forming a first buried insulating film on a semiconductor substrate;
• forming a second buried insulating film, which is formed of a material different from the first buried insulating film, on the first buried insulating film;
• exposing a part of a surface of the semiconductor substrate by removing a part of the first and second buried insulating films;
• burying a first semiconductor layer on the exposed part of the semiconductor substrate so that a horizontal level of a surface of the first semiconductor layer coincides with a horizontal level of a surface of the second buried insulating film;
• removing entirely the second buried insulating film;
• depositing a second semiconductor layer on the first semiconductor layer and the first buried insulating film;
• depositing a first insulating layer on the second semiconductor layer;
• depositing an electric charge storage layer on the first insulating layer;
• depositing a second insulating layer on the electric charge storage layer;
• depositing a gate electrode layer on the second insulating layer;
• and
• forming source and drain regions of memory cell transistors so as to implement a cell unit by an arrangement of the memory cell transistors in the second semiconductor layer.