Semiconductor apparatus and method for manufacturing the semiconductor apparatus
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki KANAYA
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Abstract
According to an aspect of the present invention, there is provided a semiconductor apparatus including a semiconductor substrate, a transistor formed on the semiconductor substrate, an insulating film disposed on the semiconductor substrate, a ferroelectric capacitor and an upper mask. The ferroelectric capacitor includes a lower electrode disposed on the insulating film, a ferroelectric film disposed on the lower electrode and an upper electrode disposed on the ferroelectric film. The upper mask includes a hard mask disposed on the upper electrode and a sidewall mask disposed on at least part of a sidewall of the hard mask.
Claims20
A semiconductor apparatus comprising:
- a semiconductor substrate;
- a memory cell transistor comprising:
- a source diffusion layer disposed on the semiconductor substrate,
- a drain diffusion layer disposed on the semiconductor substrate,
- a gate insulating film disposed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer, and
- a gate electrode disposed on the gate insulating film;
- an interlayer insulating film disposed on the semiconductor substrate and on the memory cell transistor;
- a ferroelectric capacitor comprising:
- a lower electrode disposed on the interlayer insulating film,
- a ferroelectric film disposed on the lower electrode, and
- an upper electrode disposed on the ferroelectric film;
- and
- an upper mask comprising:
- a hard mask disposed on the upper electrode, and
- a sidewall mask disposed on at least part of a sidewall of the hard mask.
A method for manufacturing a semiconductor apparatus comprising:
- forming a memory cell transistor that comprises:
- a source diffusion layer disposed on a semiconductor substrate,
- a drain diffusion layer disposed on the semiconductor substrate,
- a gate insulating film disposed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer, and
- a gate electrode disposed on the gate insulating film;
- depositing an interlayer insulating film on the semiconductor substrate;
- depositing a lower electrode layer on the interlayer insulating film;
- depositing a ferroelectric layer on the lower electrode layer;
- depositing an upper electrode layer on the ferroelectric layer;
- forming an upper mask that comprises:
- a hard mask disposed on the upper electrode, and
- a sidewall mask disposed on at least part of a sidewall of the hard mask, by performing a forming process;
- and
- collectively processing the upper electrode layer, the ferroelectric layer and the lower electrode layer by performing an etching process.
Dependencies are inferred from the claim text.