Semiconductor integrated circuit and semiconductor integrated circuit design method
AssigneeKabushiki Kaisha Toshiba
InventorHitoshi SHIGA
Life of this patent
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Abstract
The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.
Claims20
A semiconductor integrated circuit comprising:
- a semiconductor substrate formed with a plurality of transistors;
- a first wiring layer formed on said semiconductor substrate;
- a second wiring layer formed on said first wiring layer;
- a third wiring layer formed on said second wiring layer;
- a basic cell having a predetermined height and a function area, said function area including a first M0 wire formed in said first wiring layer for connecting a number of said plurality of transistors to have a specific logic function and a power supplying wire formed in a different wiring layer to said first wiring layer for supplying power to said transistors;
- and,
- a macro cell having a plurality of function areas and a height of an integral multiplication of the height of said basic cell, said macro cell including a second M0 wire formed in said first wiring layer, said second M0 wire interchanging with said power supplying wire and extending to another function area from one function area within said macro cell.
A semiconductor integrated circuit comprising:
- a semiconductor substrate formed with a plurality of transistors;
- a first wiring layer formed on said semiconductor substrate;
- a second wiring layer formed on said first wire layer;
- a third wiring layer formed on said second wire layer;
- first M0 wires formed in said first wiring layer for connecting a number of said plurality of transistors to have a specific logic function;
- a power supplying wire formed in a different wiring layer to said first wiring layer for supplying power to said transistors;
- a plurality of function areas in which at least one of said first M0 wire, said power supplying wire, and a number of said plurality of transistors connected via said first M0 wire as an internal wire are arranged;
- a second M0 wire formed in said first wiring layer for connecting a plurality of said function areas;
- a basic cell having a predetermined height and one of a plurality of said function areas;
- and,
- a macro cell including a plurality of function areas which are connected by said second M0 wire, the height of said macro cell being an integral multiplication of the height of said basic cell.
A semiconductor integrated circuit design method comprising:
- connecting a plurality of transistors which are formed in a semiconductor substrate using an M0 wire which is formed in a first wiring layer formed on said semiconductor substrate to form a basic cell having a specific logic function and a predetermined height;
- registering the cell data of said basic cell in a cell library;
- preparing a macro cell having the height of an integral multiplication of the height of said basic cell and a logic circuit larger than that of said basic cell;
- connecting said transistors with said macro cell using an M0 wire formed in said first wiring layer;
- wiring between said basic cell and said macro cell using said cell library in a state where said basic cell and said macro cell are congested, under a rule where said basic cell and said macro cell are connected by an M1 wire which is formed in a second wiring layer formed on said first wiring layer and an M2 wire which is formed in a third wiring layer formed on said second layer.
Dependencies are inferred from the claim text.