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US 2007/0195583 A1Published application
Memory with five-transistor bit cells and associated control circuit
AssigneeM2000
InventorsJean Barbier, Olvier Lepape, Philippe Piquet
Life of this patent
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Abstract
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
Claims22
A memory circuit, comprising:
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of bit cells, each bit cell formed using five transistors, with two of the five transistors forming a first inverter, another two of the five transistors forming a second inverter, the two inverters forming a bi-stable loop, and the fifth transistor serving as an access transistor, with the drain, the source and the gate of the access transistor coupled to inputs of the inverters, one of the bit lines, and one of the select lines respectively;
- and
- a controller coupled to the bit lines and the select lines, and adapted to clear all bit cells by activating all the select lines, driving all bit lines to a logic one, and causing a power cycle to be initiated on the bit cells, and to selectively set the bit cells by selectively activating the select lines and selectively driving the bit lines to logic zero.
2 more elements
An integrated circuit comprising:
- a memory block, the memory block having
- a plurality of bit lines;
- a plurality of select lines;
- a plurality of bit cells, each bit cell formed using five transistors, with two of the five transistors forming a first inverter, another two of the five transistors forming a second inverter, the two inverters forming a bi-stable loop, and the fifth transistor serving as an access transistor with the drain, the source and the gate of the access transistor coupled to inputs of the inverters, one of the bit lines, and one of the select lines respectively;
- a controller coupled to the bit lines and the select lines, and adapted to clear all bit cells by activating all the select lines, driving all bit lines to a logic one, and causing a power cycle to be initiated on the bit cells, and to selectively set the bit cells by selectively activating the select lines and selectively driving the bit lines to logic zero;
- and
- a plurality of circuit elements correspondingly coupled to the bits cells of the memory block.
4 more elements
A method comprising:
- clearing a plurality of bit cells of a memory by activating all select lines of the memory, driving all bit lines of the memory to logic one, and causing a power cycle to be initiated on the bit cells;
- and
- selectively setting the bit cells by selectively activating the select lines, and selectively driving the bit lines to logic zero.
Dependencies are inferred from the claim text.