Method for improving the alignment accuracy of semiconductor process and method of forming opening
OwnerBenjamin Szu-Min Lininventor
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Abstract
A method of improving the alignment accuracy of the semiconductor devices is described. The method is used for photolithography process, and the photolithography process is aimed at the dielectric layer covered by a hard mask layer, wherein alignment marks are formed under the dielectric layer. The hard mask layer has an absorption index and a thickness, and the product of the absorption index multiplied by the thickness is between 100 and 750. Thereby, the better range of the thickness can be determined to improve the accuracy of alignment.
Claims25
A method for improving an alignment precision for semiconductor devices, applicable for a photolithographic process, the method comprising:
- applying the photolithographic process to a dielectric layer that is covered by a hard mask layer, wherein an alignment marker is formed under the dielectric layer, and wherein the hard mask layer has an absorption index and a thickness and a product of the absorption constant and the thickness is about 100˜750;
- and
- the etching ratio of the dielectric layer to the hard mask is bigger than 5.
An alignment method for semiconductor devices, comprising:
- forming a plurality of alignment markers and a plurality of conductive lines on a substrate;
- forming a dielectric layer over the substrate and covers the alignment markers and conductive lines;
- forming a hard mask layer over the dielectric layer, wherein the hard mask layer has an absorption index and a thickness, and a product of the absorption index and the thickness is ranged between about 100˜750;
- and
- the etching ratio of the dielectric layer to the hard mask is bigger than 5;
- forming a photoresist layer over the hard mask layer;
- and
- applying a light beam onto the alignment markers to transfer a pattern of a photomask to the photoresist layer.
A method of forming an opening, applicable for interconnects of semiconductor processes, comprising:
- forming a plurality of alignment markers and a plurality of conductive lines on a substrate;
- forming a dielectric layer over the substrate, wherein the dielectric layer covers the alignment markers and conductive lines;
- forming a hard mask layer over the dielectric layer, wherein the hard mask layer has an absorption constant and a thickness, and a product of the absorption index and the thickness ranges between about 100˜750, and the etching ratio of the dielectric layer to the hard mask is bigger than 5;
- forming a photoresist layer over the hard mask layer;
- transferring a pattern to the photoresist layer according to the alignment markers;
- removing a portion of the hard mask layer by using the patterned photoresist layer as a first mask;
- removing a portion of the dielectric layer till the conductive lines are exposed by using the hard mask layer as a second mask.
Dependencies are inferred from the claim text.