Semiconductor device and related fabrication method

A semiconductor device comprising:

• a memory cell transistor disposed in a cell region of a semiconductor substrate, the memory cell transistor comprising:
• a floating gate electrode disposed on a first active region of the semiconductor substrate and comprising a first lower silicon pattern and a first upper silicon pattern, wherein the first upper silicon pattern has the same crystal structure as the first lower silicon pattern and the first active region is defined by a device isolation layer;
• a first gate insulating layer disposed between the first active region and the floating gate electrode;
• a control gate electrode disposed on the floating gate electrode, the first active region, and the device isolation layer;
• and
• an inter-gate insulating layer disposed between the floating gate electrode and the control gate electrode;
• and
• a peripheral circuit transistor disposed in a peripheral region of the semiconductor substrate, the peripheral circuit transistor comprising:
• a peripheral circuit gate electrode disposed on a second active region of the semiconductor substrate and comprising a second lower silicon pattern and a second upper silicon pattern, wherein the second upper silicon pattern has the same crystal structure as the second lower silicon pattern;
• and
• a second gate insulating layer disposed between the second active region and the peripheral circuit gate electrode.

A method for forming a semiconductor device, the method comprising:

• forming a gate electrode on a semiconductor substrate by:
• forming a lower silicon pattern on the semiconductor substrate;
• forming a device isolation layer having an upper surface disposed higher than the upper surface of the lower silicon pattern;
• and
• growing an upper silicon pattern from the lower silicon pattern through selective epitaxial growth;
• and
• forming a source/drain region on a first side of the gate electrode and in an active region of the semiconductor substrate.

A method for forming a semiconductor device, the method comprising:

• forming a floating gate electrode in a cell region of a semiconductor substrate and a peripheral circuit gate electrode in a peripheral region of the semiconductor substrate by:
• forming first and second lower silicon patterns on a semiconductor substrate, wherein the first lower silicon pattern is formed in the cell region and the second lower silicon pattern is formed in the peripheral region;
• and
• growing first and second upper silicon patterns from the first and second lower silicon patterns, respectively, through selective epitaxial growth;
• etching a device isolation layer;
• sequentially forming a preliminary inter-gate insulating layer and a control gate conductive layer on the semiconductor substrate;
• and
• patterning at least one portion of the control gate conductive layer disposed in the peripheral region and at least one portion of the preliminary inter-gate insulating layer disposed in the peripheral region to form a control gate electrode and an inter-gate insulating layer.