Method for making an integrated circuit having an embedded non-volatile memory
AssigneeFreescale Semiconductor, Inc.
InventorsChi-Nan Li, Cheong Hong
Life of this patent
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Abstract
A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidizing the gate stack at first oxidation conditions to form an oxidation layer on sidewalls of the gate stack; and oxidizing the gate stack at second oxidation conditions to form further oxidation of the oxidation layer on sidewalls of the gate stack. The second oxidation conditions are different from the first oxidation conditions.
Claims20
A method of forming an embedded non-volatile memory (NVM) comprising:
- patterning NVM gate stack layers overlying a substrate into an NVM gate stack;
- implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the NVM gate stack;
- oxidizing the NVM gate stack at first oxidation conditions to form an NVM oxidation layer on sidewalls of the NVM gate stack;
- and
- oxidizing the NVM gate stack at second oxidation conditions to form further oxidation of the NVM oxidation layer on sidewalls of the NVM gate stack, the second oxidation conditions differing from the first oxidation conditions.
A method of forming an embedded non-volatile memory (NVM) comprising:
- patterning NVM gate stack layers overlying a substrate into a NVM gate stack;
- implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent the NVM gate stack;
- oxidizing the NVM gate stack at a first temperature to form an NVM oxidation layer on sidewalls of the NVM gate stack, wherein oxidizing the NVM gate stack at the first temperature drives the dopant ions to a first depth within the substrate to form shallow source/drain extension regions and provide a first effective channel length underlying the NVM gate stack;
- and
- oxidizing the NVM gate stack at a second temperature to form further oxidation of the NVM oxidation layer on sidewalls of the NVM gate stack, wherein oxidizing the NVM gate stack at the second temperature drives the dopant ions to a second depth greater than the first depth and reduces the first effective channel length to a second effective channel length smaller than the first effective channel length, the second temperature being less than the first temperature.
A method of forming a portion of a semiconductor device comprising:
- patterning gate stack layers overlying a substrate into a gate stack;
- implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent the gate stack;
- oxidizing the gate stack at first oxidation conditions to form an oxidation layer on sidewalls of the gate stack;
- and
- oxidizing the gate stack at second oxidation conditions to form further oxidation of the oxidation layer on sidewalls of the gate stack, the second oxidation conditions differing from the first oxidation conditions.
Dependencies are inferred from the claim text.