Nonvolatile memory device and method of forming the same

A method of forming a NOR flash memory device, the method comprising:

• providing a substrate including a floating gate formed on respective active regions which are defined between device isolation regions extending in a first direction, a plurality of control gates formed on the floating gate and the device isolation regions, and a first mask formed on each of the control gates, wherein a first insulating layer is interposed between the active region and the floating gate, and a second insulating layer is interposed between the control gate and the floating gate, the plurality of control gates extending in a second direction that intersects with the first direction;
• forming a second mask extending in the second direction, wherein the second mask exposes a common source line region, and partially exposes the top surface of the first mask adjacent to the common source line region, and covers a drain region;
• removing a portion of the second mask to expose the top surface of the first mask adjacent to the common source line region;
• removing the first mask and the device isolation region disposed at the common source line region;
• and
• implanting impurity ions to form a common source line at the common source line region, and to form a drain at the drain region, after removing the second mask.

A method of forming a NOR flash memory device, the method comprising:

• forming a first gate structure on a memory region of a substrate, and a second gate structure on a peripheral circuit region of the substrate, wherein the first gate structure includes a first insulating layer, a floating gate, a second insulating layer, a control gate and a first mask which are stacked in sequence, and the second gate structure includes a gate insulating layer, a drive gate and a third mask which are stacked in sequence;
• forming a second mask such that it exposes a common source line region and partially exposes a top surface of the first mask adjacent to the common source line region in the memory region, and covers the third mask entirely in the peripheral circuit region;
• removing a portion of the second mask to expose the top surface of the first mask adjacent to the common source line region in the memory region;
• removing the first mask and the device isolation region of the common source line region in the memory region using the second mask as an etch mask;
• and
• implanting impurity ions to form a common source line at the common source line region, and to form a drain at a drain region.

A method of forming a nonvolatile memory device, the method comprising:

• forming two stacked gate structures on a substrate using a first mask;
• forming a second mask such that it exposes a first region between the two stacked gate structures, and covers a second region beyond the two stacked gate structures, wherein the second region is separated from the first region;
• removing the first mask using the second mask as an etch mask, and simultaneously removing a device isolation region of the first region;
• and
• forming a common source line in the first region and a drain in the second region.

A NOR flash memory device comprising:

• memory cells arranged in a matrix form on a substrate;
• a bit line connected to drains of the memory cells of respective columns;
• a common source line including sources of the memory cells of respective rows and source connecting units connecting adjacent sources;
• and
• a source line connected to the common source line,
• wherein the memory cell adjacent to the common source line is configured with a first insulating layer, a floating gate, a second insulating layer, and a control gate.