Method of manufacturing flash memory device
AssigneeHynix Semicondctor Inc.
InventorIn No Lee
Life of this patent
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Abstract
A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewalls of a floating gate pattern. The first spacers serve as an etch barrier layer when the isolation layers of regions exposed when a control gate and a floating gate are formed subsequently are etched, so that a second spacer is formed on sidewalls of the semiconductor substrate of an active region. Accordingly, exposure and damage of the sidewalls of the semiconductor substrate can be prevented and the reliability of devices can be improved.
Claims16
A method of manufacturing a flash memory device, the method comprising the steps of:
- forming a floating gate pattern in which a tunnel oxide layer and a first conductive layer are laminated in a first region of a semiconductor substrate, and forming isolation layers in a second region of the semiconductor substrate;
- etching the isolation layers to a predetermined thickness by a dry etch process, thus forming first spacers on sidewalls of the floating gate pattern;
- and
- forming a dielectric layer, a second conductive layer, and a hard mask layer on the entire surface, patterning the hard mask layer, the second conductive layer, and the dielectric layer to form a control gate, and etching the floating gate pattern using the control gate as a mask, forming a floating gate,
- wherein while the floating gate pattern is etched to expose the semiconductor substrate, a second spacer is formed on lateral faces of the semiconductor substrate as some of the isolation layers are etched.
A method of manufacturing a flash memory device, the method comprising the steps of:
- laminating a tunnel oxide layer and a first conductive layer in a first region of a semiconductor substrate, and forming isolation layers in a second region of the semiconductor substrate;
- etching the isolation layers to a predetermined thickness by a dry etch process, forming first spacers on sidewalls of the first conductive layer;
- forming a second conductive layer on the first conductive layer in such a way to partially overlap with the isolation layers, forming a floating gate pattern;
- and
- forming a dielectric layer, a third conductive layer, and a hard mask layer on the entire surface, patterning the hard mask layer, the third conductive layer, and the dielectric layer to form a control gate, and etching the floating gate pattern using the control gate as a mask, forming a floating gate,
- wherein while the floating gate pattern is etched to expose the semiconductor substrate, a second spacer is formed on lateral faces of the semiconductor substrate as some of the isolation layers are etched.
Dependencies are inferred from the claim text.