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US 2007/0183202 A1Published application
Memory array segmentation and methods
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
Estimating the term…
Abstract
The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
Claims60
A memory array, comprising:
- a first well region having a first conductivity type;
- a plurality of second well regions of a second conductivity type formed in the first well region, the second well regions electrically isolated from each other;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region, wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
1 more element
A memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- wherein each column of memory cells formed on each second well region is selectively coupled between a bit line and a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other.
4 more elements
A NAND memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- a plurality of word lines, each word line coupled to a row of memory cells in each second well region;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a corresponding bit line.
7 more elements
A NAND memory array, comprising:
- a substrate having a p-type conductivity;
- a first well region having an n-type conductivity formed in the substrate;
- a plurality of second well regions having the p-type conductivity formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are configured to receive the same gate voltage;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
7 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a memory array, comprising:
- a first well region having a first conductivity type;
- a plurality of second well regions of a second conductivity type formed in the first well region, the second well regions electrically isolated from each other;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region, wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
5 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- wherein each column of memory cells formed on each second well region is selectively coupled between a bit line and a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other.
8 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- a plurality of word lines, each word line coupled to a row of memory cells in each second well region;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
11 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a p-type conductivity;
- a first well region having an n-type conductivity formed in the substrate;
- a plurality of second well regions having the p-type conductivity formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are configured to receive the same gate voltage;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
11 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a memory array, comprising:
- a first well region having a first conductivity type;
- a plurality of second well regions of a second conductivity type formed in the first well region, the second well regions electrically isolated from each other;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region, wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
5 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- wherein each column of memory cells formed on each second well region is selectively coupled between a bit line and a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other.
8 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- a plurality of word lines, each word line coupled to a row of memory cells in each second well region;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
11 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a p-type conductivity;
- a first well region having an n-type conductivity formed in the substrate;
- a plurality of second well regions having the p-type conductivity formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are configured to receive the same gate voltage;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
11 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a memory array, comprising:
- a first well region having a first conductivity type;
- a plurality of second well regions of a second conductivity type formed in the first well region, the second well regions electrically isolated from each other;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region, wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
4 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- wherein each column of memory cells formed on each second well region is selectively coupled between a bit line and a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other.
7 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a first conductivity type;
- a first well region having a second conductivity type formed in the substrate;
- a plurality of second well regions of the first conductivity type formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- a plurality of word lines, each word line coupled to a row of memory cells in each second well region;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
10 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises a NAND memory array, comprising:
- a substrate having a p-type conductivity;
- a first well region having an n-type conductivity formed in the substrate;
- a plurality of second well regions having the p-type conductivity formed in the first well region, the second well regions electrically isolated from each other and the substrate;
- and
- a plurality of memory cells, arranged in row and column fashion, formed on each second well region;
- wherein corresponding rows of memory cells of the respective second well regions are configured to receive the same gate voltage;
- wherein each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series between a source select gate and a drain select gate, the source select gates forming a row of source select gates of the respective second well regions commonly coupled to a source select line, the drain select gates forming a row of drain select gates of the respective second well regions commonly coupled to a drain select line;
- wherein each source select gate selectively couples a corresponding string of floating-gate memory cells to a source line of the respective one of the second well regions, the source lines of the respective second well regions electrically isolated from each other;
- and
- wherein each drain select gate selectively couples a corresponding string of floating-gate memory cells to a bit line of the respective one of the second well regions.
10 more elements
A method of forming a memory array, comprising:
- forming a first well region having a first conductivity type;
- forming a plurality of second well regions of a second conductivity type in the first well region such that the second well regions are electrically isolated from each other;
- forming a plurality of memory cells, arranged in row and column fashion, on each second well region;
- and
- commonly coupling corresponding rows of memory cells of the respective second well regions to a word line.
2 more elements
A method of forming a memory array, comprising:
- forming a first well region having a first conductivity type in a substrate having a second conductivity type;
- forming a plurality of second well regions of the second conductivity type in the first well region such that the second well regions are electrically isolated from each other and the substrate;
- forming a plurality of memory cells, arranged in row and column fashion, on each second well region;
- coupling corresponding rows of memory cells of the respective second well regions to receive the same gate voltage;
- forming source line in each of the second well regions such that the source lines of the respective second well regions are electrically isolated from each other;
- and
- selectively coupling each column of memory cells formed on each second well region between a bit line and the source line of the respective one of the second well regions.
4 more elements
A method of forming a NAND memory array, comprising:
- doping a portion of a substrate having a first conductivity to form a first well region having a second conductivity type in the substrate;
- doping a plurality of portions of the first well region to respectively form a plurality second well regions of the first conductivity type in the first well region, wherein the second well regions are electrically isolated from each other;
- forming a plurality floating-gate memory cells, arranged in row and column fashion, on each second well region such that each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series and corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- forming a source select gate coupled to a first end of each string of series-connected floating-gate memory cells to form a row of source select gates such that the rows of source select gates of the respective second well regions are commonly coupled to a source select line;
- forming a drain select gate at a second end of each string of series-connected floating-gate memory cells to form a row of drain select gates such that the rows of drain select gates of the respective second well regions are commonly coupled to a drain select line;
- forming source line in each of the second well regions such that the source lines of the respective second well regions are electrically isolated from each other and the source lines of the respective second well regions are respectively selectively coupled to the strings of floating-gate memory cells of the respective second well regions through the select gates respectively corresponding to the strings of floating-gate memory cells;
- and
- forming a plurality bit lines in each of the second well regions such that the bit lines of each of the second well regions are respectively selectively coupled to the strings of floating-gate memory cells of the corresponding second well region through the drain select gates of the corresponding second well region.
5 more elements
A method of forming a NAND memory array, comprising:
- doping a portion of a substrate having a p-type conductivity to form a first well region having an n-type conductivity in the substrate;
- doping a plurality of portions of the first well region to respectively form a plurality second well regions having the p-type conductivity in the first well region, wherein the second well regions are electrically isolated from each other;
- forming a plurality floating-gate memory cells, arranged in row and column fashion, on each second well region such that each column of memory cells formed on each second well region is a string of floating-gate memory cells connected in series and corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line;
- forming a source select gate coupled to a first end of each string of series-connected floating-gate memory cells to form a row of source select gates such that the rows of source select gates of the respective second well regions are commonly coupled to a source select line;
- forming a drain select gate at a second end of each string of series-connected floating-gate memory cells to form a row of drain select gates such that the rows of drain select gates of the respective second well regions are commonly coupled to a drain select line;
- forming source line in each of the second well regions such that the source lines of the respective second well regions are electrically isolated from each other and the source lines of the respective second well regions are respectively selectively coupled to the strings of floating-gate memory cells of the respective second well regions through the select gates respectively corresponding to the strings of floating-gate memory cells;
- and
- forming a plurality bit lines in each of the second well regions such that the bit lines of each of the second well regions are respectively selectively coupled to the strings of floating-gate memory cells of the corresponding second well region through the drain select gates of the corresponding second well region.
5 more elements
A method of programming at least one target memory cell of an array of memory cells, comprising:
- applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other;
- applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions;
- and
- applying a third voltage to those first well regions that do not include the at least one target memory cell.
1 more element
A method of programming at least one target memory cell of an array of memory cells, comprising:
- applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other;
- applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions;
- applying a third voltage to those first well regions that do not include the at least one target memory cell;
- grounding a bit line coupled to a column of series connected memory cells that includes the target memory cell;
- and
- applying a fourth voltage to bit lines coupled to columns of series connected memory cells that do not include the target memory cell, wherein a memory cell of each column is coupled to the selected word line.
3 more elements
A method of programming at least one target floating-gate memory cell of an array of floating-gate memory cells, comprising:
- applying a programming voltage to a selected word line commonly coupled to portions of a row of floating-gate memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target floating-gate memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other;
- applying a pass voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of floating-gate memory cells not targeted for programming and respectively formed on the first well regions;
- and
- applying a third voltage substantially equal to the pass voltage to those first well regions that do not include the at least one target floating-gate memory cell;
- grounding a bit line coupled to a column of series connected floating-gate memory cells that includes the target floating-gate memory cell;
- and
- applying an inhibit voltage to bit lines coupled to columns of series connected floating-gate memory cells that do not include the target floating-gate memory cell, wherein a floating-gate memory cell of each column is coupled to the selected word line.
4 more elements
A method of programming at least one target floating-gate memory cell of an array of floating-gate memory cells, comprising:
- applying a programming voltage to a selected word line commonly coupled to portions of a row of floating-gate memory cells respectively formed on p-well regions of a plurality of p-well regions formed in an n-well region, the at least one target floating-gate memory cell coupled to the selected word line and formed on one of the p-well regions, the p-well regions electrically isolated from each other;
- applying a pass voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of floating-gate memory cells not targeted for programming and respectively formed on the p-well regions;
- and
- applying a third voltage substantially equal to the pass voltage to those p-well regions that do not include the at least one target floating-gate memory cell;
- grounding a bit line coupled to a column of series connected floating-gate memory cells that includes the target floating-gate memory cell;
- and
- applying an inhibit voltage to bit lines coupled to columns of series connected floating-gate memory cells that do not include the target floating-gate memory cell, wherein a floating-gate memory cell of each column is coupled to the selected word line.
4 more elements
A method of erasing at least one target memory cell of an array of memory cells, comprising:
- grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other;
- applying a first voltage to the first well region on which the at least one target memory cell is formed;
- and
- applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for erasing and respectively formed on the first well regions.
1 more element
A method of erasing at least one target memory cell of an array of memory cells, comprising:
- grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other;
- applying a first voltage to the first well region on which the at least one target memory cell is formed;
- applying a second voltage substantially equal to the first voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for erasing and respectively formed on the first well regions;
- and
- applying a third voltage to those first well regions that do not include the at least one target memory cell.
2 more elements
A method of erasing at least one target non-volatile memory cell of an array of non-volatile memory cells, comprising:
- grounding a selected word line commonly coupled to portions of a row of non-volatile memory cells respectively formed on p-well regions of a plurality of p-well regions formed in an n-well region, the at least one target non-volatile memory cell coupled to the selected word line and formed on one of the p-well regions, the p-well regions electrically isolated from each other;
- applying a first voltage to the p-well region on which the at least one target memory cell is formed;
- applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of non-volatile memory cells not targeted for erasing and respectively formed on the p-well regions;
- and
- applying a third voltage to those p-well regions that do not include the at least one target non-volatile memory cell.
2 more elements
Dependencies are inferred from the claim text.