Non-volatile memory device and manufacturing process

A process for manufacturing a non-volatile memory electronic device integrated on a semiconductor substrate of a first type of conductivity having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the process comprising the following steps:

• forming an insulating layer on the semiconductor substrate;
• selectively removing said insulating layer from the semiconductor substrate by means of a photolithographic technique that provides the use of a first photolithographic mask to form active areas equidistant from each other;
• forming an implanted region of a second type of conductivity in at least one of said active areas;
• forming gate electrodes of the memory cells, including one floating gate electrode and one control gate electrode;
• forming word lines of the memory matrix,
• removing from said semiconductor substrate portions of the insulating layer and forming a common source implanted region of said second type of conductivity in said semiconductor substrate, said source implanted region shared by groups of said memory cells, said common source implanted region in electric contact with said implanted region of the second type of conductivity;
• and
• forming at least one source contact in correspondence with said implanted region.

A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device comprising:

• a plurality of active areas formed on the semiconductor substrate and spaced equidistant from each other;
• said non-volatile memory cells integrated in said plurality of active areas, each non-volatile memory cell comprising a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, a group of said memory cells sharing a common source line of a second type of conductivity integrated in said semiconductor substrate;
• an implanted region of said second type of conductivity inside at least one of said plurality of active areas in electric contact with said common source line;
• at least one source contact aligned and in electric contact with said implanted region;
• and
• a plurality of drain contacts formed in correspondence with said drain regions of a group of memory cells sharing a same word line, said plurality of drain contacts aligned and equispaced with said at least one source contact.

A circuit, comprising:

• a plurality of non-volatile memory cells formed in a plurality of active areas on a substrate of first conductivity type;
• an implanted region of a second conductivity type inside at least one of the plurality of active areas and in electric contact with a source line;
• and
• at least one source contact in electric contact with the implanted region to conduct current from a drain contact formed in another active area of the plurality of active areas to the at least one source contact through the source line and the implanted region.

A circuit, comprising:

• a plurality of non-volatile memory cells formed in a plurality of active areas on a substrate of first conductivity type;
• a plurality of drain contacts formed in a plurality of drain regions of a group of the plurality of non-volatile memory cells and sharing a same word line;
• an implanted region of second conductivity type inside at least one of the plurality of active areas and in electric contact with a source line;
• and
• at least one source contact in electric contact with the implanted region to conduct current from one of the plurality of drain contacts formed in another active area of the plurality of active areas to the at least one source contact through the source line and the implanted region.