Multi-Stack Power Supply Clamp Circuitry for Electrostatic Discharge Protection
AssigneeIntel Corporation
InventorsSteven Poon, Timothy Maloney
Life of this patent
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Abstract
A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.
Claims19
An apparatus comprising:
- first circuitry to control sinking of current from a power supply node to a lower potential node in response to an electrostatic discharge event on the power supply node, the circuitry having a control node for controlling sinking operation;
- and
- second circuitry to generate a reference voltage, to buffer the reference voltage through a low impedance output, to regulate the buffering of the reference voltage by a negative feedback, and to apply the reference voltage to the control node.
A method comprising:
- providing a current sinking circuitry between a power supply node and a lower potential node;
- generating a reference voltage;
- and
- buffering the reference voltage through a buffer, controlling the buffering through a negative feedback circuit coupling the reference voltage to the buffer, and applying the reference voltage from the buffer to a control node of the current sinking circuit to couple the control node to a ground potential during an electrostatic discharge event.
Dependencies are inferred from the claim text.