High-voltage silicon-on-insulator transistors and methods of manufacturing the same
AssigneeInternational Business Machines Corporation
InventorsWilliam Ma, Jack Mandelman, Carl Radens, William Tonti
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Abstract
In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.
Claims21
A method of manufacturing a high-voltage transistor, comprising:
- providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer;
- and
- forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer;
- wherein a portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V.
A high-voltage transistor, comprising:
- a gate channel formed in a silicon-on-insulator (SOI) layer of a substrate, wherein the substrate includes a bulk silicon layer that is below an insulator layer that is below the SOI layer;
- and
- a transistor node coupled to the gate channel;
- wherein the transistor node includes a diffusion region of the transistor, and a portion of the transistor node is formed in the SOI layer;
- and
- wherein a portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V.
A substrate, comprising:
- a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer;
- and
- a high-voltage transistor, comprising:
- a gate channel formed in the SOI layer of the substrate;
- and
- a transistor node coupled to the gate channel;
- wherein the transistor node includes a diffusion region of the transistor, and a portion of the transistor node is formed in the SOI layer;
- and
- wherein a portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V.
Dependencies are inferred from the claim text.