Semiconductor circuit arrangement

Abstract

The invention relates to a semiconductor circuit arrangement having at least one first and a second field effect transistor (T1, T2), where the field effect transistors respectively have at least two active regions (AA11 to AA22) with, respectively, a source region, a drain region and an intermediate channel region, the surface of the channel regions having a gate (G11 to G22) formed on it, insulated by a gate dielectric, for the purpose of actuating the channel regions. At least one active region (AA22) of the second field effect transistor (T2) is arranged between the at least two active regions (AA11, AA12) of the first field effect transistor (T1), which results in a reduced mismatch between the two transistors, caused by temperature and local distances.

Dependencies are inferred from the claim text.