Locos self-aligned twin well with a co-planar silicon surface

A method for providing a twin well in a semiconductor device, the twin well including a P well and an N well comprising:

• providing a pad oxide;
• providing an amorphous silicon layer on the pad oxide;
• providing a silicon nitride layer on the amorphous silicon layer;
• providing a photoresist mask on a first portion of the semiconductor device, a second portion of the semiconductor device being exposed;
• removing a portion of the silicon nitride layer on the second portion of the semiconductor device;
• implanting the P well in the second portion of the semiconductor device;
• removing the photoresist mask;
• oxidizing a portion of the silicon layer on the second portion of the semiconductor device;
• removing a remaining portion of the silicon nitride layer on the first portion of the semiconductor device;
• removing a remaining portion of the silicon layer on the first portion of the semiconductor device;
• implanting the N well in the first portion of the semiconductor device;
• and
• planarizing the semiconductor device.

A method for providing a twin well in a semiconductor device, the twin well including a P-well and an N-well comprising:

• providing a nitrogen-containing oxidation stop layer;
• providing a silicon layer on the nitrogen-containing oxidation stop layer;
• masking a first portion of the semiconductor device, a second portion of the semiconductor device being exposed;
• implanting a first well in the second portion of the semiconductor device using a first dopant;
• oxidizing to completion a portion of the silicon layer in the second portion of the semiconductor device after the first well implanting;
• implanting a second well in the first portion of the semiconductor device after the oxidizing using a second dopant;
• and
• removing any remaining structure above the first and second wells of the semiconductor device after the second well implanting.

A method for providing a twin well in a semiconductor device, the twin well including a P-well and an N-well comprising:

• providing a silicon layer;
• masking a first portion of the semiconductor device, a second portion of the semiconductor device being exposed;
• providing an implant of the portion of the silicon layer using a first dopant.
• implanting a first well in the second portion of the semiconductor device using the first dopant after the implant is provided in the portion of the silicon layer;
• oxidizing a portion of the silicon layer in the second portion of the semiconductor device after the first well implanting;
• exposing the first portion of the semiconductor device;
• implanting a second well in the first portion of the semiconductor device using a second dopant after the oxidizing;
• and
• removing any remaining structure above the first and second wells of the semiconductor device after the second well implanting.

A method for providing a twin well in a semiconductor device, the twin well including a P-well and an N-well, the method comprising:

• providing a first pad oxide;
• providing a nitrogen-containing oxidation stop layer on the first pad oxide;
• providing a polysilicon layer on the nitrogen-containing oxidation stop layer;
• providing a second pad oxide on the polysilicon layer;
• providing a silicon nitride layer on the second pad oxide;
• providing a photoresist mask on a first portion of the semiconductor device, a second portion of the semiconductor device being exposed;
• removing a portion of the silicon nitride layer and a portion of the second pad oxide on the second portion of the semiconductor device;
• implanting an N-type dopant in a portion of the polysilicon layer in the second portion of the semiconductor device;
• providing the N-well in the second portion of the semiconductor device;
• removing the photoresist mask;
• oxidizing a portion of the silicon layer on the second portion of the semiconductor device to completion;
• removing a remaining portion of the silicon nitride layer on the first portion of the semiconductor device;
• performing a blanket etch;
• removing a remaining portion of the silicon layer on the first portion of the semiconductor device;
• providing the P-well in the first portion of the semiconductor device;
• and
• removing any remaining structure above the first and second wells of the semiconductor device after the second well implanting.

A semiconductor device during fabrication comprising:

• a nitrogen-containing oxidation stop layer residing on at least a first portion of the semiconductor;
• an oxidized silicon layer on the nitrogen-containing oxidation stop layer;
• a self-aligned twin well including a first well and a second well adjacent to the first well, the first well having an first well top surface and residing in the first portion of the device, the second well having a second well top surface;
• wherein the first well top surface and the second well top surface are substantially co-planar.

A semiconductor device during fabrication comprising:

• a nitrogen-containing oxidation stop layer residing on at least a first portion of the semiconductor device;
• a silicon layer on the nitrogen-containing oxidation stop layer, a portion of the silicon layer in the first portion of the semiconductor device including a first dopant;
• a first well residing in the first portion of the semiconductor device, the second well having a second well top surface;
• a second portion of the semiconductor device adjacent to the first portion of the semiconductor device, the second portion of the semiconductor device being masked.