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US 2007/0178660 A1Published application
Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
AssigneeAtmel Corporation
InventorsGayle Miller, Eric Brown
Life of this patent
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Abstract
A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.
Claims29
A method of fabricating an electrical isolation device, the method comprising:
- forming a first dielectric layer on a first surface of a substrate;
- forming a second dielectric layer over the first dielectric layer, the second dielectric layer being comprised of a substantially harder material than the first dielectric layer;
- etching through a portion of the first and second dielectric layers, thereby exposing a portion of the first surface of the substrate;
- etching a shallow trench into the substrate in a region substantially circumscribed by the exposed portion of the first surface of the substrate, the shallow trench having exposed sidewalls and a bottom region, the bottom region being substantially coplanar to the first surface;
- conformally depositing a third dielectric layer, the third dielectric layer filling the shallow trench and covering at least a portion of the second dielectric layer;
- planarizing the third dielectric layer to a level substantially coplanar with an uppermost surface of the second dielectric layer;
- forming a fourth dielectric layer over the second dielectric layer and the planarized third dielectric layer, the fourth dielectric layer being comprised of a material having a comparable hardness value as the second dielectric layer;
- etching through the third and fourth dielectric layers in a region substantially circumscribed laterally by the shallow trench;
- etching into the substrate in the region substantially circumscribed laterally by the shallow trench, the step of etching into the substrate thereby forming a deep trench in the substrate;
- and
- depositing a fifth dielectric layer, the fifth dielectric layer filling the deep trench and covering at least a portion of the fourth dielectric layer.
8 more elements
An electronic device comprising:
- at least a portion of a semiconductor substrate having thereon at least one region containing a transistor, the at least one region being laterally located in proximity to a dielectric isolation region, the dielectric isolation region having:
- a shallow trench etched into the semiconductor substrate, the shallow trench being at least partially filled with a first dielectric material, an uppermost portion of the shallow trench being essentially coplanar to a face of the substrate, the shallow trench having been formed by depositing a pad oxide on the face of the semiconductor substrate, depositing a first silicon nitride layer over the pad oxide, etching an opening into the first silicon nitride layer and the pad oxide, the opening defining a periphery of the shallow trench at the face of the substrate, etching the shallow trench into the substrate, filling the shallow trench with the first dielectric material, and conformally depositing a second silicon nitride layer over the first dielectric material and the first silicon nitride layer;
- a deep trench etched into the semiconductor substrate, the deep trench being substantially located within an area bounded laterally by an area circumscribed by the shallow trench, the deep trench being at least partially filled with a second dielectric material, the second dielectric material having a concave opening etched near an uppermost portion of the second dielectric material;
- and
- a third dielectric material filling the concave opening to a level substantially coplanar with the face of the substrate.
2 more elements
A method of fabricating an electrical isolation device, the method comprising:
- forming a first silicon dioxide layer on a first surface of a substrate;
- forming a first silicon nitride layer over the first silicon dioxide layer;
- etching through a portion of the first silicon dioxide layer and the first silicon nitride layer, thereby exposing a portion of the first surface of the substrate;
- etching a shallow trench into the substrate in a region substantially circumscribed by the exposed portion of the first surface of the substrate, the shallow trench having exposed sidewalls and a bottom region, the bottom region being substantially coplanar to the first surface;
- conformally depositing a second silicon dioxide layer thereby filling the shallow trench and covering at least a portion of the first silicon nitride layer;
- planarizing the second silicon dioxide layer to a level substantially coplanar with an uppermost surface of the first silicon nitride layer;
- forming a second silicon nitride layer over the planarized second silicon dioxide layer and the first silicon nitride layer;
- etching through the second silicon dioxide layer and the second silicon nitride layer in a region substantially circumscribed laterally by the shallow trench;
- etching a deep trench in the substrate into the substrate in the region substantially circumscribed laterally by the shallow trench;
- and
- depositing a third silicon dioxide layer, the third silicon dioxide layer filling the deep trench and covering at least a portion of the second silicon nitride layer.
8 more elements
Dependencies are inferred from the claim text.