Semiconductor device having an insulating layer and method of fabricating the same

Abstract

A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

Dependencies are inferred from the claim text.