Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages
AssigneeSamsung Electronics Co., Ltd.
InventorsKyoung-Sik Im, Han-Gu Kim, Jae-Hyok Ko, Il-Hun Son, Suk-Jin Kim
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Abstract
A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
Claims20
A clamping circuit to clamp a voltage at a first node of a first circuit, the first circuit to send and/or receive signals through a first pad, the clamping circuit comprising:
- a MOS transistor of the first circuit, a first electrode of the MOS transistor connected to the first node and a second electrode of the MOS transistor connected to a ground voltage;
- and
- a capacitive element connected between the first pad and the MOS transistor, the capacitive element storing a control voltage to turn on the MOS transistor in response to electro-static discharge (ESD).
A method of clamping a voltage of a first node of a first circuit in response to electro-static discharge (ESD), the method comprising:
- storing a voltage in a capacitance connected to a MOS transistor of a circuit in response to the ESD;
- and
- clamping the voltage of the first node by turning on the MOS transistor with the stored voltage in response to the ESD.
Dependencies are inferred from the claim text.