Transistor, memory cell and method of manufacturing a transistor

A transistor, which is at least partially formed in a semiconductor substrate having a surface, the transistor comprising:

• a first and a second source/drain regions;
• a channel connecting the first and second source/drain regions;
• a gate electrode for controlling an electrical current flowing between the first and second source/drain regions, the gate electrode being insulated from the channel by a gate dielectric;
• and
• wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.

A memory cell which is at least partially formed in a semiconductor substrate, the memory cell comprising:

• an access transistor and a storage capacitor, the access transistor transistor being at least partially formed in an active area defined in the semiconductor substrate, the active area being delimited at two sides thereof by isolation trenches filled with an insulating material, the access transistor comprising a first and a second source/drain regions;
• a channel connecting the first and second source/drain regions;
• a gate electrode for controlling an electrical current flowing between the first and second source/drain regions, the gate electrode being insulated from the channel by a gate dielectric;
• and
• wherein the channel comprises two fin-like channel portions extending between the first and second source/drain regions, the gate electrode delimiting each of the fin-like channel portion at one side thereof, each of the fin-like channel portion being delimited at the other side thereof by one of the isolation trenches.

A method of manufacturing a transistor, comprising the steps of:

• providing a substrate having a surface;
• providing isolation trenches in the substrate surface;
• filling the isolation trenches with an insulating material, thereby defining an active area, the active area being delimited at two sides thereof by isolation trenches;
• providing a first and a second source/drain regions,
• providing a channel connecting the first and second source/drain regions,
• providing a gate electrode for controlling an electrical current flowing between the first and second source/drain regions;
• providing a gate dielectric for insulating the gate electrode from the channel;
• wherein providing a gate electrode is performed in such a manner that the channel comprises two fin-like channel portions extending between the first and second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof, each of the fin-like channel portions being delimited at the other side thereof by one of the isolation trenches.

A memory cell which is at least partially formed in a semiconductor substrate, the memory cell comprising:

• means for providing an access transistor and a storage capacitor, the access transistor means being at least partially formed in an active area defined in the semiconductor substrate, the active area being delimited at two sides thereof by isolation trenches filled with an insulating material, the access transistor means comprising a first and a second source/drain regions;
• means for providing a channel connecting the first and second source/drain regions;
• a gate electrode for controlling an electrical current flowing between the first and second source/drain regions, the gate electrode being insulated from the channel by a gate dielectric;
• and
• wherein the channel comprises two fin-like channel portions extending between the first and second source/drain regions, the gate electrode delimiting each of the fin-like channel portion at one side thereof, each of the fin-like channel portion being delimited at the other side thereof by one of the isolation trenches.