SRAM cells including self-stabilizing transistor structures
AssigneeAdvanced Micro Devices, Inc.
InventorsFrank Wirbeleit, Martin Majer
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Abstract
By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and in preferred embodiments with as few as two individual transistor elements.
Claims20
A static RAM cell comprising:
- a storage transistor element for storing a bit of information, comprising:
- a p-doped drain region formed in a substantially crystalline semiconductor material;
- a p-doped source region formed in said substantially crystalline semiconductor material;
- an n-doped channel region located between and adjacent to said drain region and said source region;
- a p-doped channel region located between and adjacent to said drain region and said source region and further adjacent to the p-doped channel region;
- and
- a gate electrode to enable control of the n-doped and p-doped channel regions;
- a supply voltage terminal connecting said p-doped source region to a supply voltage source providing power to the static RAM cell;
- and
- a conductive region connecting said gate electrode to said supply voltage terminal.
A static RAM cell comprising:
- a first storage transistor element for storing a bit of information, comprising:
- a first drain region formed in a substantially crystalline semiconductor material and n-doped;
- a first source region formed in said substantially crystalline semiconductor material and n-doped;
- an first channel region, p-doped and located between and adjacent to said first drain region and said first source region;
- a second channel region, n-doped and located between and adjacent to said first drain region and said first source region and further adjacent to the first channel region;
- and
- a first gate electrode to enable control of the first and second channel regions;
- a second storage transistor element for storing said bit of information, comprising:
- an second drain region formed in said substantially crystalline semiconductor material and p-doped;
- an second source region formed in said substantially crystalline semiconductor material and p-doped;
- a third channel region, n-doped and located between and adjacent to said second drain region and said second source region;
- a fourth channel region, p-doped and located between and adjacent to said second drain region and said second source region and further adjacent to the third channel region;
- and
- a second gate electrode to enable control of the third and fourth channel regions;
- and
- a conductive region connecting said first source region, said second source region, said first gate electrode and said second gate electrode.
A computer-readable medium comprising computer-executable instructions which, when executed by a computing system, cause the computing system to simulate the behavior of a static RAM cell, the computer-executable instructions comprising:
- instructions for simulating a field effect transistor having a drain terminal, a source terminal and a gate terminal;
- instructions for simulating a first voltage controlled switch connected to one of said drain and source terminals;
- and
- instructions for simulating a second voltage controlled switch connected said first voltage controlled switch and the other of said drain and source terminals.
Dependencies are inferred from the claim text.