Circuit protection method using diode with improved energy impulse rating

A method for protecting an electrical circuit load from a high energy pulse including steps of:

• connecting a polymeric positive temperature coefficient (PPTC) resistive element in series with the electrical circuit load and an energy source;
• connecting a reverse breakdown overvoltage energy pulse absorbing semiconductor device as a shunt element between the electrical circuit load and the PPTC resistive element, said semiconductor device having a heat transfer surface sized in relation to, and in direct thermal contact with, the PPTC resistive element;
• forming the semiconductor device by:
• a. forming a planar substrate of semiconductor material having carriers of a first type of conductivity in a first, high concentration level, a first major face and a second major face opposite to said first major face, said planar substrate of said reverse breakdown semiconductor device being sized in relation to said switching element;
• b. forming a layer of semiconductor material being one of in or on said substrate adjacent said first major face, having carriers of said first type of conductivity in a second concentration level lower than said first level, and having an outer surface;
• c. forming at least one region at said outer surface extending to a first predetermined depth into said layer and having carriers of a second type of conductivity in a third concentration level to become a second-level bi-directional intrinsic conduction region as an intrinsic temperature of said at least one region is approached in response to thermal energy initially generated elsewhere in said device in response to a high energy electrical pulse;
• d. forming at least one cell at said outer surface and extending to a second predetermined depth in said substrate greater than the first predetermined depth of said at least one region and having carriers of said second type of conductivity in a fourth concentration level greater than said third concentration level to become a first-level reverse conduction region for initially generating and transferring heat to the at least one region in response to the high energy electrical pulse;
• e. forming a first electrode layer formed at and coextensive with said outer surface;
• f. forming a second electrode layer formed at and coextensive with said second major face;
• and,
• g. configuring one of the first electrode layer and the second electrode layer to be in thermal contact with the switching element for transferring heat generated by said semiconductor device in response to the high energy electrical pulse to said PPTC resistive element.

In an electrical circuit comprising an energy source, a load, and a return path, and having an overcurrent polymeric positive temperature coefficient (PPTC) resistor device in series with a supply path between the source and the load, a method for protecting against an overvoltage pulse appearing between the energy source and the PPTC resistor device, the method comprising steps of:

• (a) forming a semiconductor device with at least two doped regions including a first planar region having a relatively high dopant concentration level forming a first reverse avalanche breakdown diode junction having a relatively thin planar depletion region and a second planar region having a relatively low dopant concentration level forming a second reverse biased diode junction having a relatively thick planar depletion region;
• (b) electrically connecting the semiconductor device across the load and physically locating the semiconductor device to be in thermal contact via a heat transfer path with the PPTC resistor device;
• (c) applying an overvoltage energy pulse across the energy source of the circuit;
• (d) initially passing the overvoltage energy pulse through the overcurrent PPTC resistor device while in an unheated, untripped state to the overvoltage energy suppression semiconductor device;
• (e) initially converting the overvoltage energy pulse at the first planar region of the semiconductor device into heat and applying heat to the second planar region of the semiconductor device thereby causing it to heat up to approach an intrinsic temperature;
• (f) converting the overvoltage energy pulse at the second planar region into additional heat when the second planar region reaches the intrinsic temperature and becomes electrically conductive;
• and,
• (g) applying heat generated in the semiconductor device via the heat path to the PPTC resistor device to accelerate trip of the PPTC resistor device into a tripped, high resistance state thereby protecting the load from the overvoltage energy pulse.