Memory structure, memory device and manufacturing method thereof
OwnerMing-Tzong Yang, Wan-Chun Liao +4inventors
InventorsMing-Tzong Yang, Wan-Chun Liao, Sheng-Chin Lee, Hsiao-Lin Chen, Chien-Hao Lee, Shr-Wei Shiu
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Abstract
A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.
Claims25
A method for manufacturing a memory structure, comprising:
- providing a substrate, wherein a dielectric layer is formed over the substrate;
- forming a pattern in the dielectric layer;
- forming an amorphous silicon layer within the pattern and over the dielectric layer, and patterning the amorphous silicon layer, wherein at least a portion of the amorphous silicon layer over the pattern forms an electrode;
- forming a spacer on a sidewall of the electrode;
- and
- forming a selective hemispherical grains (SHGS) layer over a surface of the electrode and a surface of the spacer.
A memory structure, comprising:
- a substrate;
- a dielectric layer over the substrate, wherein the dielectric layer comprising a pattern;
- an amorphous layer at least formed within and over the pattern to form an electrode;
- a spacer on a sidewall of the electrode;
- and
- a selective hemispherical grains (SHSG) layer over a surface of the electrode and a surface of the spacer.
A memory device, comprising:
- a plurality of memory cells arranged in an array, wherein each of the memory cells comprises:
- a gate over a substrate;
- a source/drain region within the substrate and adjacent to the gate;
- an amorphous silicon layer over a portion of the substrate adjacent to the source/drain region to form an electrode;
- a spacer on a sidewalls of the electrode;
- and
- a selective hemispherical grains (SHSG) layer over a surface of the electrode and a surface of the spacer;
- a plurality of bit lines over the substrate, the bit lines are coupled to the source region of each of the memory cells;
- and
- a plurality of word lines, the word lines are coupled to the gate of each of the memory cells.
Dependencies are inferred from the claim text.